N.A. Starodoubstev
A. Yakovlev
S.Y. Petrov
University of Newcastle upon Tyne. 1995.
The paper describes the idea of VHDL-based synthesis of asynchronous control circuits from Signal Transition Graphs. A set of VHDL representation forms is defined which allow the designer: (1) to interact with the synthesis process more closely, using the full range of tools (simulation, visualisation etc.) available in VHDL environments. (2) to transition between the forms smoothly, sometimes using "mixed" forms, thus efficiently combining partial logic circuit implementations with event-based descriptions of the surrounding parts.